| Publication CODE |
Title |
| HD 593.1 S1 |
MICROPROCESSOR SYSTEM BUS - 8-BIT AND 16-BIT DATA (MULTIBUS I)
PART 1: FUNCTIONAL DESCRIPTION WITH ELECTRICAL AND TIMING SPECIFICATIONS |
| |
| Price Excl. VAT |
Total number of pages, tables and drawings |
|
25.00 €
|
3 P.. |
Description
Applies to interface system components, for use in interconnecting data processing, data storage, and peripheral control devices in a closely coupled configuration. This interface system contains the necessary signals to allow the various system components to interact with each other. lt allows memory and Input/Output direct memory accesses, generation of interrupts, etc. Provides a detailed description of all the elements and features that make up the system bus.
|
| Class |
C100
(GENERAL GENERALITIES)
|
| Status |
Harmonization Document |
| Situation |
Currently active
|
|
| Committee |
ISO/IEC JTC 1/SC 25
INTERCONNECTION OF INFORMATION TECHNOLOGY EQUIPMENT
|
| Responsible |
Eswaran Anirudh
Diamant Building
Bd. A. Reyerslaan, 80
B-1030
BRUXELLES - BRUSSEL
Belgique
E-mail: anirudh.eswaran@ceb-bec.be
|
| BEC Approval |
1992-06-16 |
| Registration |
96345 |
| NBN Status |
New |
|
| Date of ratification (d.o.r.) |
1992-06-16 |
| Date of availability (d.a.v.) |
1992-09-03 |
| Date of announcement (d.o.a.) |
1992-12-01 |
| Date of publication (d.o.p.) |
1993-06-01 |
| Date of withdrawal former edition (d.o.w.) |
1993-06-01 |
|
