| Publication CODE |
Title |
| IEC 62530:2011 (2011-05) |
SYSTEMVERILOG - UNIFIED HARDWARE DESIGN, SPECIFICATION, AND VERIFICATION LANGUAGE |
| |
| Price Excl. VAT |
Total number of pages, tables and drawings |
|
451.00 €
|
1251 P.. |
Description
IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
|
| Class |
C990
(IEC PUBLICATIONS IEC PUBLICATIONS)
|
| BEC Approval |
2011-05-19 |
| Registration |
115945 |
| ICS-Code (International Standards Classification) |
25.040.01
|
| NBN Status |
New |
|
| IEC publication date |
2011-05-19 |
| IEC stability date |
2023-12-31 |
| IEC last modification date |
2016-12-08 |
|
