| Publication CODE |
Title |
| IEC 61523-1:2023 (2023-10) |
DELAY AND POWER CALCULATION STANDARDS - PART 1: INTEGRATED CIRCUIT (IC) OPEN LIBRARY ARCHITECTURE (OLA) |
| |
| Price Excl. VAT |
Total number of pages, tables and drawings |
|
451.00 €
|
640. |
Description
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the 'delay calculation language' (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.
|
| Class |
C990
(IEC PUBLICATIONS IEC PUBLICATIONS)
|
| Committee |
TC 91
ELECTRONICS ASSEMBLY TECHNOLOGY
|
| Responsible |
De heer VAN HECKE Luk
|
| BEC Approval |
2023-10-11 |
| ICS-Code (International Standards Classification) |
25.040.01
, 35.060
|
| NBN Status |
New |
|
| IEC publication date |
2023-10-11 |
| IEC stability date |
2028-12-31 |
| IEC file modification date |
2023-10-11 |
| IEC last modification date |
2023-10-11 |
|
