Publication details
| Publication CODE |
Title |
| IEC 62530:2021 (2021-07) |
SYSTEMVERILOG - UNIFIED HARDWARE DESIGN, SPECIFICATION, AND VERIFICATION LANGUAGE |
| |
| Price Excl. VAT |
Total number of pages, tables and drawings |
|
451.00 €
|
1315. |
Description
IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800' SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.
|
| Class |
C990
(IEC PUBLICATIONS IEC PUBLICATIONS)
|
Status
| Status |
IEC PUBLICATION |
| Situation |
Currently active
Replaces
IEC 62530:2011
|
|
Origin
| Committee |
TC 91
ELECTRONICS ASSEMBLY TECHNOLOGY
|
| Responsible |
De heer VAN HECKE Luk
|
Approval
| BEC Approval |
2021-07-26 |
| ICS-Code (International Standards Classification) |
25.040.01
, 35.060
|
| NBN Status |
New |
|
| IEC publication date |
2021-07-26 |
| IEC stability date |
2026-12-31 |
| IEC file modification date |
2021-07-26 |
| IEC last modification date |
2021-07-26 |
|
|
