| Publication CODE |
Title |
| IEC 62530:2007 (2007-11) |
STANDARD FOR SYSTEMVERILOG - UNIFIED HARDWARE DESIGN, SPECIFICATION, AND VERIFICATION LANGUAGE |
| |
| Price Excl. VAT |
Total number of pages, tables and drawings |
|
451.00 €
|
663. |
Description
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
|
| Class |
C990
(IEC PUBLICATIONS IEC PUBLICATIONS)
|
| Committee |
TC 91
ELECTRONICS ASSEMBLY TECHNOLOGY
|
| Responsible |
De heer VAN HECKE Luk
|
| BEC Approval |
2007-11-07 |
| ICS-Code (International Standards Classification) |
25.040.01
|
|
| IEC publication date |
2007-11-07 |
| IEC last modification date |
2013-01-03 |
|
